1. Field of the Invention
The invention relates to a non-volatile semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device having memory cells which are integrated at high density comparable with an NAND type non-volatile semiconductor memory device and capable of operating with high speed random access.
2. Description of the Related Art
A non-volatile semiconductor memory to which an attention is paid as a substitute for a magnetic disk memory device or the like is constructed in a manner such that a floating gate and a control gate are laminated with an interposed electrical insulating layer onto a channel region between source and drain regions of a field effect transistor (FET) and its conductive/non-conductive state which is variable in accordance with a charging state of the floating gate is used as information of one bit to be stored. There are known various kinds of non-volatile semiconductor memories different with respect to the manner in which the charging state of the floating gate is changed. As a typical memory, there is an EEPROM in which information can be electrically erased and written by using an FN tunnel phenomenon between the floating gate and the channel region.
In a non-volatile semiconductor memory device in which the above EEPROM is used as a unit memory cell, a memory plane is constructed by two-dimensionally arranging the memory cells. With respect to an arrangement of such memory cells and a mutual connecting of them, the NOR type and the NAND type are known. Both of them have a merit and a demerit. That is, the NOR type has an advantage such that an accessing speed is high because it can be operated with random access. However, it has a drawback such that an integration density is low. To the contrary, the NAND type has high integration density, but its processing speed is slow because it cannot be operated with random access. For the details of the construction and operation of the non-volatile semiconductor memory device of the NAND type mentioned above, please see for example, JP-A-1-133290, JP-A-1-173398 and JP-A-1-282873.
As mentioned above, the non-volatile semiconductor memory devices of the NAND type and NOR type have the merits and demerits with respect to the integration density and the high operating speed.
In the conventional NAND type memory device, it is required to erase the data stored in the memory cells which are arranged near a bit line but unnecessary to be written and to rewrite therein the data before erasure. In addition, the writing operation must be simultaneously executed to all of the memory cells which are connected to a common word line. Therefore, the original data must be again rewritten into the memory cells whose original data is not to be altered. Consequently, there are also problems such that the times of erasing and writing operations increase so that the tunnel oxide films deteriorate and the reliability decreases. Furthermore, in the conventional NAND type memory device, since the tunnel voltage is supplied from the bit line, the FN tunneling to the floating gate has a tendency to occur more easily from the drain/source regions rather than the channel region and therefore the tunnel oxide film near the drain/source region easily deteriorates.